The present invention relates to integrated circuits for economically communicating between a plurality of peripheral devices and/or with a processor.
Use of MOS (metal-oxide-semiconductor) large-scale-integration (LSI) circuits in electrical devices has contributed to the cost reduction of such devices. In designing semiconductor chips, the large number of MOSTs (metal-oxide-semiconductor-transistors) together with the interconnection patterns of conductor lines therebetween must be optimized to provide the highest component density in order to reduce the required chip area to a minimum. Minimum line widths and spacing between the respective conductors composed of either polycrystalline silicon or aluminum and the MOSTs must be maintained to avoid short circuits and parasitic effects. Yet, the length of the interconnecting lines and their associated capacitances must be minimized not only to reduce chip size, but also to achieve maximum circuit operating speeds. A wide variety of trade-offs, including the necessity to minimize chip size, to increase circuit operating speed, to reduce power consumption, and to achieve acceptable reliability are involved in obtaining an optimum "layout" or arrangement of MOSTs and conductor interconnection patterns therebetween in order to obtain a MOS LSI circuit which is both economical and has acceptable operating characteristics. Often, the technical and commercial success of an electronic product utilizing MOS LSI technology hinges on the ability of the chip designer to achieve an optimum chip topography.
Some of the numerous design constraints faced by the MOS LSI chip designer include specifications for the minimum width and a spacing of diffused regions in the silicon, the minimum size required for contact openings in the insulating field oxide, the spacings required between the edges of contact openings to the edge of diffused regions, the minimum width and spacing of polycrystalline silicon conductors, the fact that such polycrystalline silicon conductors cannot coincide with the diffused regions, the minimum widths and spacings between the aluminum conductors, and the constraint that conductors on the same layer of insulated oxide cannot cross over like conductors. The high amount of capacitance associated with diffused regions and the resistances of both diffused regions and the polycrystalline silicon conductors must be carefully considered by the circuit designer and the chip designer in arriving at an optimum chip topography. Accordingly, it is an object of the present invention to provide an integrated circuit communication controller chip for effecting the transfer of data signals between remote peripheral devices and/or with a central processor in which the integrated circuit chip has a topography which provides the maximum possible circuit operating speed with the lowest possible chip size and power dissipation. It is a further object of this invention to provide an integrated chip which provides a full duplex bit synchronous communication protocol which transmits and receives Manchester encoded data utilizing either direct memory access or system access of appropriate registers over a multiplexed addressed-data bus. It is still a further object of the present invention to provide an integrated circuit communication controller chip which is very low in cost, thereby enabling its use in each of the plurality of remote peripheral devices.